The present invention relates generally to making electrical circuits and more particularly to testing electrical circuit designs. The present invention should be particularly useful in making integrated circuits.
Electrical circuits have become an integral part of many everyday devices in the home and industry. Consequently, entire industries are devoted to manufacturing electrical circuits, particularly integrated circuits. Improvements are constantly sought for the manufacturing process.
It is desirable to simulate performance of an electrical circuit before manufacture including verifying timing specifications. Timing verification can include calculating transmission delays along circuit conductors, and among combinations of the following: components, gates, input/output pads, input/output leads, etc.
Conventionally, verifying timing specifications can be an arduous, and often inaccurate, task. Although often idealized as perfectly conducting, actual wires and conductive connections are not. Instead, they provide some resistance to current flow. In addition, the wires and conductive connections may impart capacitive and inductive effects upon currents and/or signals passing through them. Collectively, these properties delay passage of currents and signals and thus distort associated rise and fall times.
Broadly speaking, three conventional timing verification schemes are commonly employed: circuit simulations, moment expansions, and combinations of circuit simulations and moment expansions. Timing approximations depend upon properties of wires and circuit elements within the electrical circuit. Because of this, timing verification schemes often intertwine with circuit reduction models which attempt to describe circuits by fewer circuit elements than in an original circuit description. By reducing a number of circuit parameters affecting a timing approximation, a computation of timing delays can be easier. Conversely, timing approximations can sometimes imply representative reduced circuits.
In the first conventional approach to timing verification, circuit simulators have circuit element values as inputs. A common input structure uses resistances and capacitances resulting from an resistive-capacitive (RC) model of the circuit or wire. Other models add in inductances (RLC) and conductances (RLCG). For some circuits, inductive-capacitive (LC) models may be useful.
RC models form chains of resistors in series and capacitors in parallel to represent wires and conductors within the circuit. Wires and other conductors have a resistance per unit length. In addition, as charge moves through the conductors, charge builds up along the conductors for short time periods implying a capacitance per unit length. The RC model's chains or "ladders" represent differential resistances and capacitances along the wires. Particularly when a width of wire varies along its length, the resistors in the chain can have differing resistances. RC models describe charges flowing into and out of the capacitors and through the resistors as a system of partial differential equations. Systems of partial differential equations are generally difficult to solve.
RC models are limited to low frequencies and currents. For higher frequencies or larger currents, or both, for a wire of a given width, they break down because other sources of signal delays arise. In essence, the wire becomes less able to quickly adjust to fast and large signal changes required by higher frequencies and larger currents.
An example of an additional source of signal delay is inductance. Essentially, differential charge buildups along the conductor cause currents to flow opposite a direction of changing current flow. For example, when current is applied to a wire, an inductive effect within the wire will induce a current in a direction opposite the applied current. When the applied current stops, i.e. is shut off, the inductive effects induce a current in the same direction as previous current flow essentially attempting to sustain the previous current flow. Inductive effects may be thought of as analogous to inertial effects resisting motion in the field of mechanics. Inductive effects are generally negligible for low frequencies and small currents. However, at high frequencies and/or large currents, inductive effects are no longer small enough to be neglected.
Higher frequencies are generally of interest as circuits are made to work faster at ever higher frequencies as in personal computers. Integrated circuits in such computers operate with fast clock signals. Ideally, clock signals are provided to all parts of the integrated circuit. Clock signals are very important and therefore are sent to parts of the integrated circuit over wires with wider effective cross sections. However, the wires are so wide that inductive effects tend to dominate delays rather than resistive or capacitive effects. Therefore, RC models are not very useful for determining delays of clock signals. This implies a need for an RLC model.
An RC, RLC, LC, or RLCG model of a wire can be input to a circuit simulator to determine circuit timing information. Circuit simulators use current constraints for nodes to create a system of ordinary differential equations between voltages and currents. Derivatives in the equations are discretized to create matrix equations. Transistors provide nonlinear amplifications, and thus their effects appear through non-linear terms in the ordinary differential equations and matrix equations.
Unfortunately, especially for long wires or many wires, a network modeled by the circuit simulators will have a huge number of resistances and capacitances as parameters. The values of R and C are approximated by resistances and capacitances per unit length based on cross-sectional shape, as well as width and depth, of a particular wire. The time for solution is roughly proportional to a number of nodes in the network raised to a power 1.5 implying very long simulation times. This is serious drawback of the circuit simulator approach.
In a second approach to timing verification, designers concentrate on inputs and outputs of circuits instead of intricacies of internal components and connections. Moment analysis is presently a popular way of doing this. A first moment is a weighted integral of an impulse response. Essentially, the first moment is the response midway through a rise of an input pulse. By comparing a time difference between the midpoint of the input voltage pulse and the first moment, a first approximation to the time delay for the wire is computed. In the art, this first approximation is called an Elmore delay. The second moment roughly corresponds to a slope of the response midway through the rise of the step input. Higher order moments give increasingly better fits of an approximate response to an actual response function.
In a basic scheme, a Laplace transform for an output voltage for a subcircuit is divided by a Laplace transform for an input voltage to a subcircuit. Each of the two Laplace transforms is a polynomial in the transformed variable typically denoted by "s." By dividing the polynomials, a polynomial expansion in s for a transfer function H(s) for the subcircuit is obtained.
The coefficients of the terms in the polynomials are the moments described above. Lower order basis polynomials have lower order moments as coefficients. For example, a constant term is the zeroth order moment. Likewise, a coefficient of a term linear in s is a first moment, and a coefficient for an s.sup.2 is a second order moment. More explicitly EQU H(s)=m.sub.0 +m.sub.1 s+m.sub.2 s.sup.2 + . . .
where m.sub.0, m.sub.1, and m.sub.2 are the zeroth, first, and second order moments.
Transfer function models generated by moment methods are often unstable. Circuit simulations using unstable models produce responses that grow without bound, even for bounded inputs. Such non-physical behavior is indicative of a "stability" failure. In addition, the subcircuit's transfer function is combined with other quantities in other subcircuits to integrate the reduced subcircuit with other subcircuits. For example, an inverse of the transfer function may be added to a resistance for a resistor in another subcircuit with the sum subsequently inverted. Unfortunately, combining even a stable moment-method transfer-function model with other circuit components, or other stable transfer-function models, can lead to an overall unstable model. This is a failure of "absolute stability."
The moment approach also breaks down for inductive effects. If a wire only has resistive and capacitive properties, a response to a step input is strictly increasing. Therefore, the integral of the response over time is strictly increasing as a function of time. When inductances are introduced, the response can be negative at first resulting from induced currents opposite the direction of an applied a current as described above. As the response to the applied step impulse current reaches its steady value, corresponding to a constant current of the step, the response may vary because of induced currents. This effect is termed "ringing" or "undershoot" and "overshoot."
In a third approach to timing verification, some designers combine the first two approaches in circuit-to-circuit reduction schemes. This approach uses moment calculations to replace R's and C's in circuit simulator calculations with fewer "reduced" R's and C's. By making a moment expansion for the original circuit or a subcircuit, reduced elements can be obtained which have the moments of the original circuit or subcircuit. Circuit simulations then obtain timing information from the reduced resistances and capacitances. A drawback of this scheme is that circuit elements in the reduced circuit are approximate and only match true values for an actual reduced circuit having the same functionality as the original RC circuit to a certain order.
FIGS. 1A-C illustrate a sample circuit-to-circuit reduction. In FIG. 1A, a wire 30 is connected to two other wires 32 and 34 and form a subcircuit 31 of an electrical circuit. Wire 30 is represented by a "ladder" or "chain" of resistors 36 in series and capacitors 38 in parallel in a representative circuit 35 in FIG. 1B. A sum of resistances for resistors 36 approximately equals a total resistance for the wire 30, and a sum of capacitors 38 approximately equals a total capacitance for the wire 30. The resistances 36 and capacitances 38 are computed from geometry of the wire 30. Similarly, wire 32 is represented by a ladder of resistors 40 and capacitors 42, and sums of resistances and capacitances equal total resistance and total capacitance for the wire 32. The wire 34 is represented by a chain of resistors 44 and capacitors 46. As with wires 30 and 32, a sum of resistors 44 equals the total resistance of the wire 34, and a sum of the capacitances equals the total capacitance of the wire 34.
A sample reduced or modified representative circuit 50 is formed by circuit-to-circuit reduction from the representative circuit 35. The reduced circuit 50 is shown in FIG. 1C. Wire 30 is represented in the reduced circuit 50 by fewer resistors 56 than resistors 36 in the original circuit 35. There are also fewer capacitors 58 than capacitors 38 in the original circuit. In like fashion, wire 32 has fewer resistors 60 and capacitors 62 than in the representative circuit 35, and wire 34 has fewer resistors 64 and capacitors 66 than in the representative circuit 35.
In summary, the conventional timing verification and circuit-to-circuit reduction schemes applied to wires have several drawbacks. Circuit simulators are very slow for many practical problems. Moment methods require detailed knowledge of circuit connections to simulate driving the electrical circuit and receiving response at specified points. As just noted, they are generally unstable. Both circuit simulators and moment methods have difficulty handling distributed circuit quantities such as resistance and capacitance per unit length on a wire. They also cannot model in a parametrized way coupling between wires in close proximity to each other which are not physically electrically connected. In addition, traditional circuit-to-circuit reduction is computationally very intensive and time consuming and approximates values for reduced circuit elements only to low order. Even so, the reduced circuits tend to still be rather large for most situations of practical interest.